Ве молиме користете го овој идентификатор да го цитирате или поврзете овој запис: http://hdl.handle.net/20.500.12188/32233
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dc.contributor.authorStefkovski, Vojdanen_US
dc.contributor.authorMileski, Dimitaren_US
dc.contributor.authorGusev, Marjanen_US
dc.date.accessioned2025-01-09T10:18:18Z-
dc.date.available2025-01-09T10:18:18Z-
dc.date.issued2024-11-26-
dc.identifier.urihttp://hdl.handle.net/20.500.12188/32233-
dc.description.abstractThis paper investigates the impact of loop unrolling on CUDA matrix multiplication operations’ performance across NVIDIA GPUs. We benchmarked both basic and unrolled kernels with varying unroll factors (2, 4, 8, and 16) and CUDA block sizes (8, 16, and 32) on matrices ranging from 128 × 128 to 4096 × 4096. Using two GPUs, the GeForce RTX 4060 and GTX TITAN X, we analyze how unrolling factors impact execution time. Our findings indicate that loop unrolling, particularly with factors of 8 and 16 and a block size of 32, yields significant performance gains on larger matrices. These results confirm loop unrolling as an effective optimization technique for CUDA matrix operations, providing insights for developers to enhance computational efficiency across different GPU architectures.en_US
dc.publisherIEEEen_US
dc.subjectProcessor scheduling , Graphics processing units , Computer architecture , Performance gain , Distance measurement , Telecommunications , Registers , Computational efficiency , Kernel , Optimizationen_US
dc.titleLoop Unrolling Impact on CUDA Matrix Multiplication Operationsen_US
dc.typeArticleen_US
dc.relation.conference2024 32nd Telecommunications Forum (TELFOR)en_US
dc.identifier.doi10.1109/telfor63250.2024.10819077-
dc.identifier.urlhttp://xplorestaging.ieee.org/ielx8/10818990/10818991/10819077.pdf?arnumber=10819077-
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dc.identifier.lpage4-
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item.grantfulltextopen-
Appears in Collections:Faculty of Computer Science and Engineering: Conference papers
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