Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12188/19633
Title: VHDL IP cores ontology
Authors: Zdraveski, Vladimir 
Trajanov, Dimitar 
Issue Date: 2013
Publisher: Faculty of Computer Science and Engineering, Ss. Cyril and Methodius University in Skopje, Macedonia
Conference: CIIT 2013
Abstract: Recently, the hardware description languages (HDL) are part of the most of hardware design processes and the HDL components are the main intellectual property (IP) of the producers of IC's. The large companies have internal databases and moreover whole code sub-versioning repositories, but however the easiness of code reuse is still quite low and there is almost no intelligence in the storage systems. Contributing to the improvement of the hardware design process, essentially based on the reuse of previously written cores, and utilizing the Semantic Web technologies, we propose a basic ontology for semantic annotation of VHDL components, that also contains the most frequently used component types and their "is-part-of"-dependencies, providing a knowledge base for classification and automated composition of predefined IP cores.
URI: http://hdl.handle.net/20.500.12188/19633
Appears in Collections:Faculty of Computer Science and Engineering: Conference papers

Files in This Item:
File Description SizeFormat 
10CiiT-52.pdf357.14 kBAdobe PDFView/Open
Show full item record

Page view(s)

32
checked on Apr 19, 2024

Download(s)

7
checked on Apr 19, 2024

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.