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http://hdl.handle.net/20.500.12188/19633
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Zdraveski, Vladimir | en_US |
dc.contributor.author | Trajanov, Dimitar | en_US |
dc.date.accessioned | 2022-06-27T11:16:02Z | - |
dc.date.available | 2022-06-27T11:16:02Z | - |
dc.date.issued | 2013 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.12188/19633 | - |
dc.description.abstract | Recently, the hardware description languages (HDL) are part of the most of hardware design processes and the HDL components are the main intellectual property (IP) of the producers of IC's. The large companies have internal databases and moreover whole code sub-versioning repositories, but however the easiness of code reuse is still quite low and there is almost no intelligence in the storage systems. Contributing to the improvement of the hardware design process, essentially based on the reuse of previously written cores, and utilizing the Semantic Web technologies, we propose a basic ontology for semantic annotation of VHDL components, that also contains the most frequently used component types and their "is-part-of"-dependencies, providing a knowledge base for classification and automated composition of predefined IP cores. | en_US |
dc.publisher | Faculty of Computer Science and Engineering, Ss. Cyril and Methodius University in Skopje, Macedonia | en_US |
dc.title | VHDL IP cores ontology | en_US |
dc.type | Proceeding article | en_US |
dc.relation.conference | CIIT 2013 | en_US |
item.grantfulltext | open | - |
item.fulltext | With Fulltext | - |
crisitem.author.dept | Faculty of Computer Science and Engineering | - |
crisitem.author.dept | Faculty of Computer Science and Engineering | - |
Appears in Collections: | Faculty of Computer Science and Engineering: Conference papers |
Files in This Item:
File | Опис | Size | Format | |
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10CiiT-52.pdf | 357.14 kB | Adobe PDF | View/Open |
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