Programmable processing element for crypto-systems on FPGAs

Abstract

This paper presents the design and analysis of an areaefficient programmable processing element (PPE) for implementing diverse cryptographic systems and diverse bitwidths (currently 16, 32, and 64). To evaluate the effectiveness of our design, we implement π-Cipher and BMW on the PPE. π-Cipher is a new algorithm for authenticated encryption that offers advantages over AES-GCM and is a candidate in the CAESAR competition. BMW is a SHA-3 candidate and is used for the QuarkCoin crypto-currency. The design of the programmable processing element PPE requires the use of on-chip memory for storing the internal structure of one round of the π-function as well as for the PPE instruction logic. With the new processing element, on Xilinx Virtex-5, we implemented the PPE in just 227 slices, achieving a throughput of 1.17 Gbps/block for the π-Cipher 64-bit version and 256 Mbps/block for BMW at 250 MHz. The PPE is designed to be modular, for inclusion in larger FPGA designs or SoCs, and is also easily extended to wider bit-widths.