Reducing the number of instructions
Date Issued
2000-06-13
Author(s)
Popovski, G
Mitrevski, P
Abstract
The purpose of this article is to reduce the number of instructions while executing in
processor. We analyse memoiy address dependent instructions and eliminate the ada'ress
generation processing if the address was previously calculated For standard RISC? WIWand inorder superscalar processor we introduce a solution where the MI (Reduction of Memory
Instructions) Algorithm is perfomzed in the compile stage and aa'hess dependent instructions do
not enter the processor at all. For out-qfdr&r superscalm processors we introduce two solutions,
theJirst one when these instructions me not issued at all and the second solution when these
instructions are issued only in a reservation station without execution unit. All these solutions
improve the behaviour of thc processor for at least 10% since the processor does not executes
these instructions.
processor. We analyse memoiy address dependent instructions and eliminate the ada'ress
generation processing if the address was previously calculated For standard RISC? WIWand inorder superscalar processor we introduce a solution where the MI (Reduction of Memory
Instructions) Algorithm is perfomzed in the compile stage and aa'hess dependent instructions do
not enter the processor at all. For out-qfdr&r superscalm processors we introduce two solutions,
theJirst one when these instructions me not issued at all and the second solution when these
instructions are issued only in a reservation station without execution unit. All these solutions
improve the behaviour of thc processor for at least 10% since the processor does not executes
these instructions.
Subjects
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