Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12188/17251
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dc.contributor.authorAnchev, Nenaden_US
dc.contributor.authorGushev, Marjanen_US
dc.contributor.authorRistov, Sashkoen_US
dc.contributor.authorAtanasovski, Blagojen_US
dc.date.accessioned2022-04-05T08:56:22Z-
dc.date.available2022-04-05T08:56:22Z-
dc.date.issued2013-05-20-
dc.identifier.urihttp://hdl.handle.net/20.500.12188/17251-
dc.description.abstractMatrix-Matrix multiplication (MMM) is widely used algorithm in today’s computations and researches. Many techniques exist to speed up its execution. In this paper, we analyze the performance of MMM varying matrix size in order to determine its behavior and the region where it provides the best performance. We also determine the best speedup and efficiency in parallel implementation for different CPU architectures since cache architecture and organization is very important for MMM performance. Intel i7 and AMD Opteron CPUs are used as an environment. Several achieved results are expected, but there are also many unexpected. Superlinear speedup (speedup greater than the number of used threads) and the efficiency greater than 100% are achieved for each parallel implementation only on AMD Opteron. We observe regions with performance discrepancy for all three parameters for both CPUs.en_US
dc.publisherIEEEen_US
dc.subjectHPC, CPU, Cache, Memory, Superlinear Speedupen_US
dc.titleIntel vs AMD: Matrix Multiplication Performanceen_US
dc.typeProceeding articleen_US
dc.relation.conference2013 36th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO)en_US
item.grantfulltextopen-
item.fulltextWith Fulltext-
crisitem.author.deptFaculty of Computer Science and Engineering-
crisitem.author.deptFaculty of Computer Science and Engineering-
Appears in Collections:Faculty of Computer Science and Engineering: Conference papers
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