Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12188/17249
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dc.contributor.authorRistov, Sashkoen_US
dc.contributor.authorGushev, Marjanen_US
dc.contributor.authorAnchev, Nenaden_US
dc.contributor.authorAtanasovski, Blagojen_US
dc.date.accessioned2022-04-05T08:56:08Z-
dc.date.available2022-04-05T08:56:08Z-
dc.date.issued2012-09-
dc.identifier.urihttp://hdl.handle.net/20.500.12188/17249-
dc.description.abstractMemory access is the bottleneck of all computations. CPU cache is introduced to speed up accessing reused and local data. Matrix multiplication is the most common representative of many linear algebra algorithms which performance directly depends of the cache. Many cache parameters exist and impact the overall computing performance such as cache type, line, size, level, associativity, and replacement policy. Therefore an optimal architecture to execute certain compute and memory intensive algorithm is desirable in most applications. We have developed MMCacheSim simulator to predict matrix multiplication performance on particular existing or non-existing multiprocessor. MMCacheSim simulates the execution time and number of cache misses that matrix multiplication algorithm performs with particular matrix size and element size executing on processor with different cache size, line, level associativity, and replacement policy.en_US
dc.subjectCPU Cache, Multiprocessor, HPC, Simulationen_US
dc.titleMMCacheSim: A Highly Configurable Matrix Multiplication Cache Simulatoren_US
dc.typeProceeding articleen_US
dc.relation.conferenceICT Innovationsen_US
item.fulltextWith Fulltext-
item.grantfulltextopen-
crisitem.author.deptFaculty of Computer Science and Engineering-
crisitem.author.deptFaculty of Computer Science and Engineering-
Appears in Collections:Faculty of Computer Science and Engineering: Conference papers
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