Ве молиме користете го овој идентификатор да го цитирате или поврзете овој запис:
http://hdl.handle.net/20.500.12188/17249
Наслов: | MMCacheSim: A Highly Configurable Matrix Multiplication Cache Simulator | Authors: | Ristov, Sashko Gushev, Marjan Anchev, Nenad Atanasovski, Blagoj |
Keywords: | CPU Cache, Multiprocessor, HPC, Simulation | Issue Date: | сеп-2012 | Conference: | ICT Innovations | Abstract: | Memory access is the bottleneck of all computations. CPU cache is introduced to speed up accessing reused and local data. Matrix multiplication is the most common representative of many linear algebra algorithms which performance directly depends of the cache. Many cache parameters exist and impact the overall computing performance such as cache type, line, size, level, associativity, and replacement policy. Therefore an optimal architecture to execute certain compute and memory intensive algorithm is desirable in most applications. We have developed MMCacheSim simulator to predict matrix multiplication performance on particular existing or non-existing multiprocessor. MMCacheSim simulates the execution time and number of cache misses that matrix multiplication algorithm performs with particular matrix size and element size executing on processor with different cache size, line, level associativity, and replacement policy. | URI: | http://hdl.handle.net/20.500.12188/17249 |
Appears in Collections: | Faculty of Computer Science and Engineering: Conference papers |
Files in This Item:
File | Опис | Size | Format | |
---|---|---|---|---|
ICTI_2012_submission_44.pdf | 282.04 kB | Adobe PDF | View/Open |
Записите во DSpace се заштитени со авторски права, со сите права задржани, освен ако не е поинаку наведено.