Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12188/17247
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dc.contributor.authorRistov, Sashkoen_US
dc.contributor.authorGushev, Marjanen_US
dc.contributor.authorAnchev, Nenaden_US
dc.contributor.authorAtanasovski, Blagojen_US
dc.date.accessioned2022-04-05T08:24:41Z-
dc.date.available2022-04-05T08:24:41Z-
dc.date.issued2012-09-12-
dc.identifier.urihttp://hdl.handle.net/20.500.12188/17247-
dc.description.abstractMatrix multiplication is compute intensive, memory demand and cache intensive algorithm. It performs O(N3) operations, demands storing O(N2) elements and accesses O(N) times each element, where N is the matrix size. Implementation of cache intensive algorithms can achieve speedups due to cache memory behavior if the algorithms frequently reuse the data. A block replacement of already stored elements is initiated when the requirements exceed the limitations of cache size. Cache misses are produced when data of replaced block is to be used again. Several cache replace policies are proposed to speedup different program executions. In this paper we analyze and compare two most implemented cache replacement policies First-In-First-Out (FIFO) and Least-Recently-Used (LRU). The results of the experiments show the optimal solutions for sequential and parallel dense matrix multiplication algorithm. As the number of operations does not depend on cache replacement policy, we define and determine the average memory cycles per instruction that the algorithm performs, since it mostly affects the performance.en_US
dc.publisherSpringer, Berlin, Heidelbergen_US
dc.subjectFIFO, HPC, LRU, Performance, Speedupen_US
dc.titleProceedings of the ITI 2013 35th international conference on information technology interfacesen_US
dc.typeProceeding articleen_US
dc.relation.conferenceInternational Conference on ICT Innovationsen_US
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crisitem.author.deptFaculty of Computer Science and Engineering-
crisitem.author.deptFaculty of Computer Science and Engineering-
Appears in Collections:Faculty of Computer Science and Engineering: Conference papers
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