Hardware Implementation of IP Packet Filtering in FPGA

Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12188/16634

Title:	Hardware Implementation of IP Packet Filtering in FPGA
Authors:	Cholakoska, Ana Efnusheva, Danijela Kalendar, Marija
Keywords:	FPGA, IP Header Fields Extracting, IP Packet Filtering, Network IDS Systems
Issue Date:	2019
Publisher:	Anhalt University of Applied Sciences
Conference:	International Conference on Applied Innovation in IT, ICAIIT 2019
URI:	http://hdl.handle.net/20.500.12188/16634
Appears in Collections:	Faculty of Electrical Engineering and Information Technologies: Conference Papers

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