An Improvement in the Convergence of Superscalar Processors
Journal
2020 43rd International Convention on Information, Communication and Electronic Technology (MIPRO)
Date Issued
2020-09-28
Author(s)
DOI
10.23919/mipro48935.2020.9245144
Abstract
Modern processors include reservation stations to host instructions that are waiting to be sent to the execution units. Responsive to exception event, instructions in reservation stations that are younger than the instruction executed with exception need to be flushed. In this paper, we propose a mechanism for flushing instructions from reservation stations. The proposed mechanism determines relative age between instructions in reservation stations and instruction executed with exception by comparing reorder buffer indexes assigned to the instructions in reservation stations with the tail pointer of the reorder buffer and with the reorder buffer index of the instruction executed with exception. Instructions younger than the instruction executed with exception are flushed from the reservation stations.