Faculty of Computer Science and Engineering
Permanent URI for this communityhttps://repository.ukim.mk/handle/20.500.12188/5
The Faculty of Computer Science and Engineering (FCSE) within UKIM is the largest and most prestigious faculty in the field of computer science and technologies in Macedonia, and among the largest
faculties in that field in the region.
The FCSE teaching staff consists of 50 professors and 30 associates. These include many “best in field” personnel, such as the most referenced scientists in Macedonia and the most influential professors in the ICT industry in the Republic of Macedonia.
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Item type:Publication, Privacy preserving synchronization of directed dynamical networks with periodic data-sampling(Elsevier BV, 2025-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Contribution to the Quasigroup Based Error-Detecting Code(IEEE, 2023-07-19)In the last years we have developed few error-detecting codes based on quasigroups. One of them is the code which is a subject of this paper. The previous analyses of the code shows that the code has very high probability of detecting transmission errors. We have previously identified so-called best class of quasigroups of order 4, with the highest probability of detecting errors when the coding process is performed with a quasigroups of order 4. But, there is one more class of quasigroups of order 4, second-best class, whose quasigroups give approximately equal probability of undetected errors as the quasigroups from the best one. Therefore, we proceeded with the examination of the code when it uses quasigroups from this second-best class of quasigroups of order 4. In this paper we will analytically obtain the second important parameter of every error-detecting code, i.e. the number of errors that the code surely detects when for coding it uses a quasigroup from this second-best class of quasigroups of order 4. At the end we will conclude whether the quasigroups from these top two classes have overall equal ability to detect errors with this code. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A Comparison of GEC Tools for Grammatical Error Correction in English(IEEE, 2025-06-02) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Evaluation of Scalability and Multi-tenancy: A Use-Case(IEEE, 2021-11-23) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, What makes Dew computing more than Edge computing for Internet of Things(IEEE, 2021-07)A lot of research and development activities have been referencing to edge and dew computing solutions for IoT applications, but without determining the deep distinction between these two architectural approaches. Furthermore, there is no clear explanation if dew computing is a special case of edge computing or the opposite. In this paper, we analyze the features of post-cloud architectures to build an IoT solution and clarify the main differences between dew and edge computing approaches. Although the provided analysis covers IoT solutions, still the same principles can be applied more generally. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Benchmarking Virtual Machine and Container-based Services for DNN Training(IEEE, 2021-11-23); Kjirovski, KirilContainerized infrastructure is becoming the leading strategy for deployment and operation of software components including trending neural networks. Training neural networks requires computational resources and complex software environments with a lot of dependencies. In this regard, containers can solve some of the software related challenges. We perform benchmarks to compare the performances of containers inside a virtual machine and a bare metal model for training three artificial neural networks on two leading cloud providers. The results show negligible performance drawback for using containers in the stack tested on Google Cloud and clear performance advantages in Amazon Web Services. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator(Institute of Electrical and Electronics Engineers (IEEE), 2022-02); ; Zhang, YanlongThis brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise and ultra-low power performance. By employing the mixed switching scheme, the segmented capacitive digital-to-analog converter (CDAC) arrays as well as the synchronous data-weighted averaging (DWA) calibration block, the proposed SAR ADC can operate from 1.8 V down to 0.8 V at 20–200 kS/s. The designed ADC is fabricated in a 0.18- μm CMOS process and the measurement results show the proposed SAR ADC achieves an SNDR of 65-dB with power consumption of 647 nW from a 0.8 V power supply at 20 kS/s. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Serverless and Deviceless Dew Computing: Founding an Infrastructureless Computing(IEEE, 2021-07)Cloud computing provides computing resources on a subscription basis, targeting infrastructure (hardware), platform (hardware plus system software), and software. Although post-cloud computing models bring the computing closer to the user, they still use the same principles to provide computing resources to the requestor. While building applications, designers face challenges to specify optimal computing resources. Serverless computing is the answer from cloud providers to take care about the availability of computing resources to relieve programmers suggesting to concentrate on programming functions to be executed as a service. Deviceless approach goes even further allowing functions to be executed on nearby devices instead of servers. In this sense, we define infrastructureless computing as the architectural approach where the programming is isolated from specifying the infrastructure requirements, as a general platform of serverless and deviceless computing. Moreover, the generalization of this approach initiates a new computing model where the functions are executed on a lower architectural layer instead of the higher one. For example, an edge server or device, can activate smart devices on the dew computing level and distribute computing to devices (embedded systems) on a lower architectural level. An example may be activating smartphones to perform computing tasks while being charged overnight, or using smart devices installed in cars, while parked in a parking lot. This concept enhances the dew computing architectural model making it a sophisticated platform for future architectural models. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A Method to Detect Ventricular Fibrillation in Electrocardiograms(IEEE, 2021-09-27) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, TPC-H Benchmark Q3, Q6 and Q12 Sequential, OpenMP Parallel and CUDA Parallel Implementation(IEEE, 2021-09-27); Arsenovski, SimeIn the last decade or two, parallel computing has solved a myriad of problems when it comes to speeding up the problem-solving process. To deliver the necessary acceleration of their product, application developers have turned to CUDA-powered GPU parallel processing. One of the many uses of the well-known NVIDIA parallel computing platform CUDA is to enhance the performance of problems whose root comes from speeding up database queries. The fundamental focus of this paper is evaluating the performance of different parallelizing techniques using the TPC-H benchmark. This is achieved by parallelizing the ‘SELECT’ queries that the benchmark offers using the Open Multi-Processing (OpenMP) API (Q3, Q6, and Q12 in particular), then parallel on the GPU using the previously mentioned CUDA platform. Lastly, comparing the GPU's performance with both sequential instruction execution and parallel instruction execution on a CPU. This implementation resulted in speedup ratios ranging from 2 to 4 when analyzing the CPU-parallel code and ranging from 10 up to 558 when analyzing the GPU - parallel code.