Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12188/17225
Title: EDUCacheIC: Interactive and Collaborative Successor of the EDUCache Simulator
Authors: Ristov, Sashko 
Atanasovski, Blagoj
Anchev, Nenad
Gushev, Marjan 
Keywords: Cache; Computer Architecture and Organization; CPU; Education; Multiprocessor
Issue Date: 25-Sep-2013
Publisher: IEEE
Conference: 2013 International Conference on Interactive Collaborative Learning (ICL)
Abstract: Introducing our EDUCache simulator [1] in the Computer Architecture and Organization course increased the students willingness to learn more details about CPU cache memory. A positive experience of students interest to work on laboratory exercises with our EDUCache simulator lead us to develop an EDUCacheIC, a new interactive and collaborative version of EDUCache simulator. EDUCacheIC offers the students to work in a group with one student member of the group having a role as a teacher. The student - teacher creates a CPU architecture and tasks for other students in the group. This interactive and collaborative simulator will improve the learning and teaching process of the Computer Architecture and Organization course reducing the teacher's efforts during the laboratory exercises.
URI: http://hdl.handle.net/20.500.12188/17225
Appears in Collections:Faculty of Computer Science and Engineering: Conference papers

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