Проектирање и практична реализација на RISC-базирана мемориско-центрична процесорска архитектура и нејзина примена

Abstract

The technological advances in the area of computer hardware and software resulted in a wide range of fast and cheap single- or multi-core processors, compilers, operating systems and programming languages, each with its own benefits and drawbacks, but with the ultimate goal to increase the overall computer system performances. Although the number of transistors on a chip had doubled roughly every 18 months, according to the Moore's law, there is still difficult to improve the performances of the sequential processors, and even of the parallel multi-core and multi-processor shared-memory systems. The main reason for this resides in the well known Von- Neumann bottleneck which occurs during the communication between the processor and the main memory into a standard processor-centric computer system. This problem has been reviewed by many scientists, which proposed different approaches for improving the memory bandwidth and latency. A brief review of these techniques and a deep analysis of various memory-centric systems that implement different approaches of merging or placing the memory near to the processing elements are given in this PhD thesis. Within this analysis, the advantages, disadvantages and application (purpose) of several well-known memory-centric systems are discussed. The aim of the research presented in this PhD thesis is to design and implement novel RISC (Reduced Instruction Set Computing)-based memory-centric processor architecture in order to provide stronger merge between the processor and the memory that holds the data that should be processed, and thus to avoid the occurrence of processor-memory bottleneck. Тhe basic idea of this research is to develop a processor that integrates the memory into the same chip die and that allows direct access to the memory data, without the use of general purpose registers (GPRs) and cache memory, as redundant resources in the system. Contrary to the other memory/logic merged chips, which mostly use the standard memory hierarchy model for data access, the proposed RISC-based memory-centric processor directly addresses the data into the on-chip memory, without the use of explicit Load and Store instructions and includes specialized control unit that performs 4-stage pipelining of instructions (without MEM - memory access phase), allowing every (arithmetical, logical, branch, control) instruction to be completed in а single tact cycle. Besides that, the proposed RISC-based memory-centric processor implements a specialized logic that provides direct access to non word-aligned data words. This logic can be used for network packet headers parsing in order to allow direct access to packet header fields, when the proposed RISC-based memory-centric processor is applied in network processing. The proposed RISC-based memory-centric processor is described in VHDL (Very High Speed Integrated Circuit Hardware Description Language) and then implemented in Virtex7 VC709 FPGA (Field Programmable Gate Array) board, by means of Xilinx VIVADO Design Suite. The simulation timing diagrams and the FPGA synthesis (implementation) reports for the proposed RISC-based memory-centric processor are discussed and analyzed in this PhD thesis. Besides the hardware prototype, a dedicated instruction-level simulator for the proposed RISC-based memory-centric processor architecture is also developed. This simulator is purposed to examine the processor's state and to present the number of executed processor cycles, during the execution of various programs. Therefore, the given simulator is used to explore the applicability of the proposed RISCbased memory-centric processor architecture in different types of applications (with diverse arithmetical intensity according to the Roofline model), with particular emphasis on applications that require large data bandwidth, such as packet processing in networks. The purpose of this analysis is to determine the type of applications for which the proposed RISC-based memorycentric processor architecture brings performance improvements, in comparison with other similar processor architectures. The main contribution of this research is the development of novel RISC-based memorycentric processor architecture, which provides: faster and simplified access to data in memory, higher internal memory bandwidth, avoidance of redundant copy operations and data transfers into registers and cache memory, and removal of the memory management complexity that is involved by the operating system. All these modifications make the proposed RISC-based memorycentric processor applicable for execution of programs that are characterized with high and/or medium arithmetical intensity, mainly because the proposed processor provides direct access to the memory, avoiding the time consuming stalls which occur during the data exchanges between the registers and the cache memory into the standard memory hierarchy. Additionally, the proposed RISC-based memory-centric processor can be applied in high throughput network packet processing, because it includes a specialized logic for parsing of network packet headers, which can significantly simplify and speed-up the packet handling and processing. Besides these contributions, it is important to emphasize that as a result of this research a complete hardware and software prototype of the proposed RISC-based memory-centric processor is built.