Please use this identifier to cite or link to this item:
http://hdl.handle.net/20.500.12188/24198| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Mishev, Anastas | en_US |
| dc.contributor.author | Gushev, Marjan | en_US |
| dc.date.accessioned | 2022-11-07T09:49:36Z | - |
| dc.date.available | 2022-11-07T09:49:36Z | - |
| dc.date.issued | 2001 | - |
| dc.identifier.uri | http://hdl.handle.net/20.500.12188/24198 | - |
| dc.description.abstract | Usage of simulators in the process of processor development is very common thing. Simulators are used mainly in designing new techniques to improve performances. Main purpose of all these techniques is extracting more parallelism by resolving dependencies. Register renaming is a mechanism for coping with false data dependencies. Exploring the design space for register renaming gives plenty of opportunities to improve the overall performance. | en_US |
| dc.publisher | Institute of Informatics, Faculty of Natural Sciences and Mathematics, Ss. Cyril and Methodius University in Skopje, Macedonia | en_US |
| dc.subject | register renaming, superscalar processor, out of order, simulation | en_US |
| dc.title | Exploring the Register Renaming Design Space Using the Supersim Simulator | en_US |
| dc.type | Proceedings | en_US |
| dc.relation.conference | CIIT 2001 | en_US |
| item.grantfulltext | open | - |
| item.fulltext | With Fulltext | - |
| crisitem.author.dept | Faculty of Computer Science and Engineering | - |
| crisitem.author.dept | Faculty of Computer Science and Engineering | - |
| Appears in Collections: | Faculty of Computer Science and Engineering: Conference papers | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 2CiiT-05.pdf | 571.53 kB | Adobe PDF | View/Open |
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