Please use this identifier to cite or link to this item:
http://hdl.handle.net/20.500.12188/19646| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Zdraveski, Vladimir | en_US |
| dc.contributor.author | Dimitrovski, Andrej | en_US |
| dc.contributor.author | Trajanov, Dimitar | en_US |
| dc.date.accessioned | 2022-06-27T11:30:18Z | - |
| dc.date.available | 2022-06-27T11:30:18Z | - |
| dc.date.issued | 2014 | - |
| dc.identifier.uri | http://hdl.handle.net/20.500.12188/19646 | - |
| dc.description.abstract | A huge part of the HDL development process is spent on testing and simulation. Supporting the idea of a testbench design automation, we present a module of the HDL IP Cores system, integrated with a client-side eclipse plug-in, as an automatic testbench search engine embedded inside the designer's native programming environment. The concept is extended with the use of a simulator for compatibility verification and existing results ranking improvement. | en_US |
| dc.subject | automation, HDL, search, testbench, verification | en_US |
| dc.title | HDL IP Cores System as an Online Testbench Provider | en_US |
| dc.type | Proceeding article | en_US |
| dc.relation.conference | Proceedings of the 5th Small Systems Simulation Symposium 2014, Nish, Serbia, | en_US |
| item.grantfulltext | open | - |
| item.fulltext | With Fulltext | - |
| crisitem.author.dept | Faculty of Computer Science and Engineering | - |
| crisitem.author.dept | Faculty of Computer Science and Engineering | - |
| Appears in Collections: | Faculty of Computer Science and Engineering: Conference papers | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 20 HDL IP Cores System as an Online Testbench Provider.pdf | 175.23 kB | Adobe PDF | View/Open |
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