A 16-Bit Reconfigurable Encryption Processor for p-Cipher
Date Issued
2016-05-23
Author(s)
Mihajloska Trpcheska, Hristina
El-Hadedy, Mohamed
Gligoroski, Danilo
Kulkarni, Amit
Stroobandt, Dirk
Skadron, Kevin
Abstract
This paper presents an improved hardware implementation of a 16-bit ARX (Add, Rotate, and Xor) engine for one of the CAESAR second-round competition candidates, πCipher, implemented on an FPGA. π-Cipher is a nonce-based authenticated encryption cipher with associated data. The
security of the π-Cipher relies on an ARX based permutation function, which is denoted as a π-function. The proposed ARX engine has been implemented in just 266 slices, which includes
the buffers of the input and the output. It can be clocked at 347 MHz. Also, in this paper, a message processor based on the proposed ARX engine is introduced. The message processor
has been implemented in 1114 slices and it can be clocked at 250 MHz. The functionality of the proposed ARX engine was verified on the Xilinx Virtex-7. The new design of the ARX
engine allows for almost four times speedup in performance while consuming only 17% larger area than previously published work. We extend our message processor implementation by using parametrized reconfiguration technique after which an area reduction of 27 slices is observed.
security of the π-Cipher relies on an ARX based permutation function, which is denoted as a π-function. The proposed ARX engine has been implemented in just 266 slices, which includes
the buffers of the input and the output. It can be clocked at 347 MHz. Also, in this paper, a message processor based on the proposed ARX engine is introduced. The message processor
has been implemented in 1114 slices and it can be clocked at 250 MHz. The functionality of the proposed ARX engine was verified on the Xilinx Virtex-7. The new design of the ARX
engine allows for almost four times speedup in performance while consuming only 17% larger area than previously published work. We extend our message processor implementation by using parametrized reconfiguration technique after which an area reduction of 27 slices is observed.
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